Complete and Improved FPGA Implementation of Classic McEliece

Complete VLSI Implementation of Improved Low

This thesis presents a complete VLSI design of improved low complexity chase (LCC) decoders for Reed-Solomon (RS) codes. This is the first attempt in published research that implements LCC decoders at the circuit level. Based on the joint algorithm research with University of Hawaii, we propose several new techniques for complexity reduction in LCC decoders and apply them in the VLSI design for...

An Improved Wavelet Filtering Algorithm and Its FPGA Implementation

The de-noising of sensor data has become an important to research. Since the traditional de-noising method can’t achieve successful de-noising effect and the software-only method never meets a high real time capability. In this paper, we illustrate a novel threshold function based on the wavelet hard and soft threshold function. It is unlike ordinary function, which has overcome the defect such...

Improved Number Plate Localisation Algorithm and its Efficient FPGA Implementation

Abstract—Number plate localisation is a very important stage in an Automatic Number Plate Recognition (ANPR) system and is computationally intensive. This paper presents a low complexity with high detection rate number plate localisation algorithm based on morphological operations together with an efficient multiplierless architecture based on that algorithm. The proposed architecture has been ...

Botan’s Implementation of the McEliece PKC

Toward Secure Implementation of McEliece Decryption

We analyse the security regarding timing attacks of implementations of the decryption in McEliece PKC with binary Goppa codes. First, we review and extend the existing attacks, both on the messages and on the keys. We show that, until now, no satisfactory countermeasure could erase all the timing leakages in the Extended Euclidean Algorithm (EEA) step. Then, we describe a version of the EEA nev...